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4. System ESD Simulation

4.1 System ESD simulation know-how 

For a new design system (without experience from testing), it is not easy to prevent or estimate ESD in advance by a simulatio. Not only ESD, but EMI is also true. This is because the prerequisite for accurate simulation is that you must be aware of what phenomena you want to observe, whether the IC/ material/ component/ mechanism within the relevant range can get the model, or if there is a way to build an approximate model.

First, we have to analyze the system to converge the problem scope, list the most likely EMC three-factor (noise source, coupling path/interference path and receiver/victim), and try to reproduce the phenomenon by simulation. If it works, then you can find the root cause and solution with simulation. Therefore, applying simulation to EMC predection or post-event analysis is absolutely feasible, and is also a method for many large companies (such as Samsung, Apple, Google...) to accumulate their energy and improve competitiveness.

The existing simulation technology can only do contact discharge, but not air discharge.  There is no EM field solver can simulate the arc caused by high-pressure dissociation of water in air so far. Therefore, if you want to simulate a different mechanism latch bending to reduce the ESD injection, it is still not possible.

Some people may still have doubts, because the energy transfer did be seen when the ESD gun is simulated away from the object 1mm [20]. To further explain, this is only the effect of mutual capacitive/inductive coupling between the two conductors, and  it does not include the arcing (flashover) effect of the humidity (water molecules) ionization in the air. The following image is taken from the Industry Council on ESD Target Level, White Paper Part II [10]

4.2 System ESD paper [8] 

If you have been a senior EMC engineers for more than three years, or more than five years of senior hardware engineers, may have this experience: sometimes PCB seperated plane can enhance system ESD tolerance (for the PCB is usually under connector, and connected/grounded to the chassis), but sometimes it makes the system ESD and EMI worse. Why?

Refer to [8] guide of this paper , or next section 4.3 to validate these phenomena with simulation

4.3 System ESD simulation

4.3.1 ESD discharges to ground plane. Simulate by HFSS v15 

When ESD discharges on ground plane, the plane with higher impedance (with slot or EBG pattern) will get better system ESD immunity. It is caused from the damping effect of plane impedance.

4.3.2 ESD discharge to a microstrip line. Simulate by HFSS v15  

On the other hand, when ESD discharges on transmission line with discontinuous reference plane, it will get worse system ESD immunity. It is due to high frequency component of signal (as ESD energy) will get more ringing (reflection) for discontinuous transmission line.

Segmentation will increase the impedance of the plane path, which in theory will improve the ESD immunity, but if it makes the transmission line placed on different reference planes, the system SI/PI/esd/EMI will become worse as well. In addition, the ground plane segmentation changes the path of ESD discharging, and makes larger difference potential for the different areas, that is also the reason of the system ESD getting worse.

4.3.3 Vertical Indirect Discharge Simulation with 2019 R1 HFSS

4.3.3.1 Use ESD Gun from 3.1 

When the square metal ring (ESD victim) is awayfrom the vertical metal plate 0.1m (defined by IEC), the induced current/voltage peak on the metal ring is approximately 38mA/38nV.

Looking at the upper left figure, the VCP maintains high E=1~5e+4V/m at the 70~80ns. It is due to the VCP grounding path has two 470k ohm resistors in series. Compare with the upper right figure (short the two 470k ohm resistors), it's E-filed attenuates faster obviously.

4.3.3.2 Use ESD Gund from 3.2 

It is very close to 4.3.3.1, but the maximum of I(ESD_tip) is smaller than 4.3.3.1. This value (6A) is less than 7.5A, and I actually feels that it is a more reasonable result.

At 13ns, every I(ESD_tip) even from different ESD gun models suddenly rise. Let's observe H-field, you can see a current round-trip flows in the ESD ground strap. The single-direction transfer time is about 6ns, and the round-trip cycle of 12ns. It just works like 4.3.3.1 I(ESD_tip) behavior from 1ns, a small current appears periodically every 12ns. Refer to 5.9

5. Q&A 

5.1 Any relationship between IC and System ESD?

Ans：Reference [10] 2012 p.17, there is a comparison table Fig.1, and it claims the system ESD is independent from IC ESD. That is, even the immunity of IC ESD does well, it does not represent the system ESD will be good as well, becaue system ESD considers more factors. Please note that such arguments and comparisons are highly controversial : 1. This comparison is based on only HBM of IC ESD, not including MM, CDM, and IC latch-up performance. 2. It does not compare with the same system conditions/environment either. Try to imagine a situration, for low-level consumer products, to add one more 0.1uF capacitor are concerned very much, if the competitor's IC solution directly replaces yours on the same board, and gets better ESD immunity capability, can you still feel that there is nothing need to do for IC performance improvement? Therefore, this question should be asked in another way: under the same system design conditions , IC ESD and system ESD is directly related?

I fully agrees that "More factors need to be considered for system ESD immunity. To get the system ESD good, not just make sure the IC strong enough, FW robust, strong WDT (watch dog timer), system level PCB layout and components selected ... all of these are important. As long as you have a few years of actual IC mass production experience, it is not difficult to find a good IC ESD tolerance, it did help the IC market competitiveness absolutely. In further, only increasing IC ESD (including HBM,MM,CDM) and Latch-up capabilities with minimum IC costs addition, that can get competitive. Otherwise, it is just in the matter of debating which side (by IC or system) to cover EMS problem. The answer is simple, only the one who overcomes the problem gets the better profit. If you push the responsibility out, you are waitting to be eliminated.

Why IC ESD has three kinds of test methods HBM, MM and CDM? It is because they qualify different discharge models and discharge paths, especially the CDM can find out the IC internal weakness that make the ESD immunity worse due to signals across different pwr/gnd domains.

Some people may still question my statement：IC ESD concerns IC damage, however system ESD concerns system function downgrade, they are different. Why did I say that they are related? Let's explain it from how the ESD protection circuit work inside the IC die level. In fact, it is also all about the venting of noise (RC push MOS transient path), clamping voltage ...ect. , the same concept as system protection. If the system ESD is not good enough, there may be system function downgrade, or IC function downgrade. When the different models encounter problems in mass production, you don't know which one is the system dominate, which one is the IC dominate, so both of them should be taken care well.

To argue if there is a direct relationship between IC ESD and system ESD, the broader discussion is that if there is a direct relationship between "IC's noise tolerance" and "system noise tolerance". Currently the system noise tolerance tests are mainly defined by ESD, EFT ans Surge test.

5.2 How to plot S-parameter under Transient mode? 

Ans：Only "Transient" solve + "Network Analysis" can plot S-parameter from [Report Rectangular] with [Spectral] solution setting.

5.3 How to plot Field result for transient solve?

Ans：To plot the field of transient analysis, some setting have to be done first
          -- select surfaces, and add list from [Modeler\ List\ Create\] to plot fields result
          -- set "save field" in setup window

5.4 Can lump RLC boundary be used on a solid object?

Ans：For HFSS frequency domain, it is ok, but for time domain solve, it permits "rectangle" sheet only for "Lump RLC boundary"

5.5 Can HFSS simulate CDM(Charge Device Mode) ESD?

Ans：HFSS can't simulate CDM alone, because HFSS can't charge Q(charge) to nonconductor. However, HFSS+Circuit model can do it [21].

CDM is that a lot of static charge accumulates on a device (the entire device of non-conductor + conductor, such as package) first, and discharges to the nearby conductor. It causes a large current flowing from the charged body itself instantaneously and damage the device.

5.6 What differences are between the 3 kinds of HFSS ESD Gun?

Ans：The method of section 2.1 is established by the concept of two-stage discharge of arms and body. It's behavior is similar to section 2.2 [3][4], and I_peak appears fast and sharp. Althought the method of sec. 2.3 has been cited in the IEEE many times since 2003 ([2][6][7] the same batch of research teams), but it's I_peak appears slower and thicker.

5.7 What factors will affect the speed of HFSS Transient Solver?

Ans：

There are two processes for transient analysis, one is the mesh and the other is the transient sweep. The time of former one is related to the size and complexity of the 3D geometry, however the time of latter one is related to the characteristics of the energy field changing with time. For the problem of intense energy changes in a short period (a broadband problem), because it requires a smaller time step, the transient sweep time will be longer.

For HFSS transient analysis, the delta error can be set from 0.1 to 0.01, and the smaller the value, the longer the simulation time. I am used to making refine mesh at least 3~5 times to avoid oscillations of time domain (not converged).

5.8 To observe voltage/current of ESD, should we check E-filed or H-field? 

Ans：Where the voltage (drop) is larger, the electric field is stronger as well, and the flow of charge produces a magnetic field. So we look at E-field for ESD voltage distribution, and look at H-field for ESD current distribution.

Seeing the distribution of voltage bright spots and the distribution of current bright spots have different meanings, and whether the system components die in overvoltage (EOS) or overcurrent (ESD) is another problem. In general ESD testing, component damage (Class D) is often caused from the transient overcurrent breaks down the IO, or the ESD triggers the Latch-up in the CMOS IC to damage the IC.

5.9 When ESD discharge, the grounding end of ESD gun strap will shine or not?  

Ans：When performing ESD simulation with 3D EM tool, and looking at E-field, there is only a bright spot at ESD tip end. However, if you look at H-field, both of the discharge end and the ground end have bright spots.

In the HFSS, no matter which method to implement ESD gun model, when doing system ESD simulation, it will be seen that while ESD gun is discharging (at 1 ns), there is also a current flowing from ESD gun through the ground strap to the reference ground (at 1ns~7ns). The reason is：a real ESD gun charges the 150pF capacitor by a relay/DC voltage and discharge with a two-stage model. In the FEM environment, the front switch (V114) in the equivalent circuit of 2.2 directly replaced by a 2KV step waveform, which causes the voltage at one end of C3 (150pf) to be pulled up instantaneously, and the voltage at the other end of C3 is also pulled high, that causes a current flowing on the ESD strap.

5.10 What is the difference between Lump Port or Voltage Source for Transient solver? 

Ans：HFSS Help says that transient analysis works with Wave port, Lump port, Voltage source, Current source and Incident wave, and the simulated result of voltage source defined by dataset is the same as that of Designer circuit. However the result of driven terminal lump port defined by the same dataset will be obviously larger than voltage source.

For more information on this issue, see the [Excitations in Time Domain] in the HFSS Help. Figure 1 below shows how does the transient simulation of the driven terminl lump port work. By Kirchhoff's voltage law, the circuit is equivalent to the Figure 2, which is the way voltage source and circuit simulation engine approach. So, if you use Terminal Port (as lump port in driven terminal) in HFSS Transient, the input voltage defined by dataset should be *0.5 volt.

5.11 How to detect ESD soft failures (Class B) and find the root cause to improve? 

Ans：Samsung published an IEEE Transaction paper [9] in 2011. As I said earlier, the key point of EMC simulation is that it is necessary to narrow-down check for converging the problem first by system analysis (as Step 5 or the figure below), then model the problems and try to reproduce EMC issues by simulation.

5.12 What is the difference between Composite Excitation and Network Analysis of Transient solver?  

Ans：

5.12.1 For "Composite Excitation", different ports can have different excitation sources. The  type of excitation sources can be set separately in the Excitation property (which can be defined differently from each other), and are calculated simultaneously in the simulation.

5.12.2 For "Network Analysis", all excitation sources are the same. The type of the excitation source is moved to the Solution Setup as below and set up with the same excitation definition.

Just "Composite Excitation" can use [Dataset] as an excitation pattern. It can't export S-parameter and can't support differential pair, and it just support "Discrete sweep", not support "Interpolate sweep".

"Composite Excitation" solve wideband field faster(special for multi-port excitation), but it doesn't for S-parameter export or differential pair.

5.13 ESD gun is charged by a voltage source, however the discharge tip waveform is defined by voltage or current?

Ans：ESD gun outputs a current pulse (current source), and the regulation defines the current waveform of discharging too (as  defined in section 1.1). However, when the instrument manufacturer or measurement center is doing the ESD Gun calibration, in fact, they directly measure voltage through the attenuator by the oscilloscope. The current pulse is attenuated by 30dB and  enters the oscilloscope to measure the rise time [14].

The TARGET in the above picture is a very important device. It looks like the picture below. The middle is the current output point and is surrounded by a circle of grounding points. It is a coaxial connector.

The configuration of the test system is shown in the figure below：ESD gun output is transmitted to the TARGET, and it is connected to the oscilloscope through a attenuator.[14]