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Home > ANSYS Designer 教學 > DDR3 Simulation using SPICE Model
The article is intended to use Designer v7.0 to do DDR3 simulation with encrypted HSPICE model.
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Use Micron SPICE Model
2.2 Modify SPICE (.sp and .inc)
2.3 Include Library (.cnr)
2.4 Import SPICE (.inc) in Designer
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Use Hynix SPICE Model
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Use Nanya SPICE Model
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5.1 最新版的IBIS 5.0特點?
5.2 選SPICE或IBIS model的評估原則是?
5.3 SPICE與IBIS model的主要差異來源是?
5.4 Micron DDR3為何加了這麼多的on-die de-cap?
5.5 為何有些.Options可以包在.subckt內，有些則不行?
5.6 使用encrypted HSPICE，還能使用DesignerSI的QuickEye或VerifyEye嗎?
5.7 如何測試SPICE model的特性? 比如測試IC內有沒有含on-die cap? Vref input有沒有內含RC filter?
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Download Micron、Hynix、Samsung、Nanya DDR3 SPICE Model
1.1 Micron MT41J128M16JT-107 (實測OK)
1.2 Hynix DDR3 H5TQ1G83AFR (實測波形怪怪的)
1.3 Samsung K4B1G0446G (需要憑證才能驅動)
1.4 Nanya南亞 (筆者還驅動不起來)
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Use Micron SPICE Model
Read "v89c_hspice_readme.txt" to know .inc files are encrypted net-list and .sp files are deck files (test bench).
The file "v89c_model.cnr" and encrypted net-list (.inc) are required to be in the same directory to simulate.
The .LIB statements (in .cnr file) select the simulation corners：TYP_xxxx、SLOW_xxxx、FAST_xxxx, where xxxx=1066~2133 Mbps
On-Die De-capacitor：VCCQ/VSSQ decoupling capacitance is included in the DQ and DQS models
DQ = 522pF
DQS/DQS# = 1044pF
Total = 522pF x 16(DQ) + 1044pF x 2(DQS/DQS#) = 10.44nF
Set "rfat_vccq" parameter high in "v89c_model.cnr" to remove this capacitance
There are two key points：
On-die de-cap. (decoupling capacitor) plays an important role for DDR3
Most of IC venders provide encrypted SPICE model, so users must have HSPICE license to run the encrypted SPICE file.
若您沒有指定的IO model做評估/練習，筆者推薦Micron的IBIS與SPICE model是不錯的選擇。因為Micron的DDR model建的很齊全，語法寫的又正規，使用文件與模擬、測試波形驗證也很完整(有模擬與量測數據比對，IBIS與SPICE模擬波形比對)，非常適合初學者正確觀念的建立。
從Micron的官方測試報告中，我們發現即使速度到2133MHz，IBIS與SPICE模擬的SI結果幾乎是一樣的。但讀者請注意，這裡考慮的只有SI，還不含PI的模擬比對，這部分筆者將陸續撰文說明當中的差異。
2.2 Modify SPICE (.sp and .inc)
Open "v89c_dq.sp" first with an editor, and copy some [.OPTIONS][.PARAM] and paste them to the top of "v89c_dqbuff.inc".
Then save the modified "v89c_dqbuff.inc" as "v89c_dqbuff_modify.inc".
2.3 Include Library (.cnr)
[Circuit] \ [Add Reference Data] \ [Add Library/Include Reference]
2.4 Import SPICE (.inc) in Designer
2.4.1 [Project] \ [Insert Circuit Design]
2.4.2 [Tools] \ [Import SPICE Components], import the "v89c_dqbuff_modify.inc"
2.4.3 Drag "v89c_dqbuff" into circuit edit window
到目前為止，讀者檢視.sp的說明，已經可以在Designer內開始透過對每根接腳拉高或拉低，來設定此IO的特性 ：
[EMR9 EMR6 EMR2]=[0 1 1] means 40 ohm ODT
[EMR5 EMR1]=[0 0] means 40 ohm drive strength
這樣電路圖最後會接的很複雜，若把控制訊號的高低設定狀態與library都包在.sp內，直接import .sp當subckt會更簡潔。
2.5 Import Simple SPICE (.sp) in Designer
把原本的"v89c_dq.sp"另存一個"v89c_dqbuff_6pin.sp"，並作如下的修改：to set ODT_40 enable, and DDR3_2133 typical
.subckt v89c_dqbuff_6pin IN VREF PKG_OUT vss vcc enout // 把整個spice model用subckt包起來
...
*.TRAN 0.005ns '12*per'
*.LIB "v89c_model.cnr" TYP_1066
*.LIB "v89c_model.cnr" TYP_1600
*.LIB "v89c_model.cnr" TYP_1866
.LIB "v89c_model.cnr" TYP_2133 // include library...
VODT_EMR6 EMR6 0 DC = vss // set 40 ohm ODT
VODT_EMR6 EMR6 0 DC = vcc
VODT_EMR2 EMR2 0 DC = vcc...
Vodt_en odten 0 DC = vcc // enable ODT
...
*Ven enout 0 DC = vcc
...
*.PARAM datarate = 1066.67E6
*.PARAM datarate = 1333.33E6
*.PARAM datarate = 1600.00E6
*.PARAM datarate = 1866.67E6
.PARAM datarate = 2133.33E6...
**** Vin toggles the DQ at the datarate specified above
*Vin IN 0 LFSR gnd vcc delay dataslew dataslew datarate 1 [5 2]...
Xi0 RCVR_OUT PAD CKD CKDF EMR1 EMR2 EMR5 EMR6 EMR9 ENOUT IN ODTEN VREF vss vcc vccq vssq v89c_dqbuff
...
*Rtt pkg_out vtt r=25 // Disable external Thevenin Termination
...
*.END
.ENDS v89c_dqbuff_6pin
[Tools] \ [Import SPICE Components], import "v89c_dqbuff_6pin.sp"
2.6.1 Connect the SPICE model in step 2.5 , install HSPICE and link to HSPICE from Design to run encrypted SPICE file.
[Circuit] \ [Add HSPICE Solution Setup] \ [Transient Analysis]
2.6.2 Troubleshooting HSPICE (for ANSYS EBU R15 and last version)
Verify that HSPICE runs correctly outside of ANSYS. HSPICE must work correctly on its own before it can be run inside the ANSYS framework.
For Windows PCs, Set the [AD_HSPICE_INSTALLDIR] environment variable to the full path of the HSPICE executable. For example, on Windows where the HSPICE executable is hspice.exe, set AD_HSPICE_INSTALLDIR to be:
C:\synopsys\Hspice_H-2013.03-SP2\WIN64\hspice.exe
2.6.3 Simulation Result (with 1000mils microstrip line)
這波形看來ODT 40是有作用的，模擬結果如預期
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Use Hynix SPICE Model
Read "readme.txt" first to know that .net are encrypted net-list files and .spi are deck files (test bench).
To run simulation, "Device_Resistor_Diode.model"、"SKEW.LIB"、"PVT_Condition.LIB" and "dqbuf.net" are required to be in the same directory.
看不出有多少on-die de-cap.在vddq to vssq
把原本的"dqbuf.spi"另存一個"dqbuf_modify.spi"，並作如下的修改：to set ODT_40 enable, and DDR3_1333 typical
*************** Option Define ************************************
*.options acct nomod dccap nopage dcap post=1
.options accurate=1 scale=1u
****************************************************************
.subckt dq_sub_7pin doi doe dq_ball rxen vdd vref vss...
*.tran 0.1ns 'period*7'
************************ Power Define ****************************
*.global vdd gnd vss vssi vddq vssq
...
****************** Variables for input data **************************
.param datarate=1333E+6...
******** din buffer(receiver) disabled ********************************
*vrxen rxen 0 dc 0 $ Write Data In Disabled
...
******** ODT Operation *******************************************
VODTEN ODTEN 0 dc pvdd $ ODT enable
*VODTEN ODTEN 0 dc 0 $ ODT disable
**************** odt description ***********************************
** Disable 120 60 40 30 20_ohm ***
VODT<9> ODT<9> 0 dc 0 $0 0 0 0 pvdd pvdd
VODT<6> ODT<6> 0 dc pvdd $0 pvdd 0 pvdd 0 0
VODT<2> ODT<2> 0 dc pvdd $0 0 pvdd pvdd pvdd 0***************** dout driver enabled ******************************
*vdoi doi 0 pulse(0 pvdd delay trf trf pulsewidth period)
*vdoe doe 0 dc pvdd $ Write Data In Disabled
*vdoe doe 0 dc 0 $ Write Data In Enabled
******** driver strength control *************************************
** 34_ohm 40_ohm **
VDriver<5> Driver<5> 0 dc 0 $0 0
VDriver<1> Driver<1> 0 dc 0 $pvdd 0
****************************************************************...
*.end
.ENDS dq_sub_7pin
5.1 最新版的IBIS 5.0特點?
Ans：主要是增加了IBIS-AMI：提供方便的加密模擬(通用於各模擬平台)、支援IC內的訊號等化器(EQ)行為的模擬
5.2 選SPICE或IBIS model的評估原則是?
5.3 SPICE與IBIS model的主要差異來源是?
Ans：1. SPICE能以transistor level描述CMOS電壓轉態的暫態過程中，此時PMOS、NMOS都有些微導通，IO會從Vcc抽較大的電流 2. SPICE能以transistor level描述電路間細微的RLC寄生效應
5.4 Micron DDR3為何加了這麼多的on-die de-cap?
Ans：到了DD3-1666以上的速度，SI設計需要考慮的有效頻寬達到3G~5G，此時board level或package level的高頻電容都無法起有效的de-coupling作用，on-die de-cap才能有最短的去耦路徑、最小的loop inductance，在高頻才能達到有效的de-coupling performance
5.5 為何有些.Options可以包在.subckt內，有些則不行?
Ans：被.subckt包起來的.Options，相當於是不起作用的，所以如果是關於模擬精度、收斂設定、單位定義相關的options，最好是放.subckt外面。另外，.subckt內不能有.end、.alter、.global
5.6 使用encrypted HSPICE，還能使用DesignerSI的QuickEye或VerifyEye嗎?
Ans：因為QuickEye或VerifyEye是以Designer的Nexxim模擬引擎處理，所以無法對encrypted HSPICE做QuickEye或VerifyEye Analysis.
5.7 如何測試SPICE model的特性? 比如測試IC內有沒有含on-die cap? Vref input有沒有內含RC filter?
Ans：試著在Vqqd、Vref上灌入耦合雜訊成份(如100MHz sinwave)，看看DQ output的輸出訊號頻譜上，載有多大的100M耦合能量
[1] Optimizing On Die Decap in a System at Early Stage of Design Cycle, DesignCon2014.
-- 很有系統觀的研究手法，IO Cload會影響on die decap的效果(because of resonance effect)，非常好的一篇研究[2] C. Iorga, Experimental Optimization of Decoupling Capacitors in FPGA by On-Die Measurement, DesignCon2012.
[3] C. Iorga, Troubleshooting Power Integrity Problems in PLD Electronic Systems by Embedded Measurement, DesignCon2012.