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本文始於2021，以2021R2示範SPISim生成IBIS模型的流程(三種方法)。不論是不是IC設計公司的工程師，從現在起您都可以輕易的產生、檢視、修改與驗證IBIS模型，當然您建的模型所生成的波形有多準，取決於一開始所能掌握的資訊有多少與是否正確。

  1. 從內建模塊產生IBIS模型 (快速)

  2. 從系統規格產生IBIS模型 (簡單)

  3. 從SPICE模型生成IBIS模型 (精確)

  4. 問題與討論

    4.1 What does "Rfixture" parameter in step 2.2 mean?

    4.2 How to generate IBIS with ODT(On-Die Terminator)?

    4.3 How to generate differential IBIS model from SPICE netlist?

    4.4 IBIS內的波形有min/type/max三種corner，有些還有slow/fast，該如何理解?

  5. 參考

SPISim - 於2020年起合併於ANSYS Electronic Entriprise，八分鐘速成。

Open SPISim from [Tools] \ [SPISim] in AEDT

Change Module Type from [VPro : Waveform/S-Parameter ...] to [MPro : General modeling ...]

  1. 從內建模塊產生IBIS模型

此流程特別適合於拿不到IC IBIS模型且對建模毫無經驗的系統廠商，用以快速產生一個IBIS模型。

1.1 [IBIS] \ [Generate spec. IBIS model]

1.2 Select an IBIS model from the pre-build templates

1.3 Check Rising/Falling waveform of the IBIS generated by SPISim

[IBIS] \ [IBIS file(s) Inspector] to open the IBIS (ibis_v1p2_z30_temp.ibs), which is just generated by SPIsim

上圖左邊[Rising Waveform]與[Falling Waveform]各有兩組，分別是透過50 ohm接到供電電壓VDDQ(1.2V)與接地VSS(0V)的波形，這是IBIS定義的波形觸發條件。

1.4 Compare the IBIS generated by SPISim with the original generated by Micron

  1. 從系統規格產生IBIS模型

此流程特別適合於拿不到IC IBIS模型的系統廠商，用以產生一個可以指定上升/下降緣斜率的的IBIS模型。

2.1 [IBIS] \ [Generate spec. IBIS model]

2.2 Set some parameters to generate IBIS model

Slew-rate rising/falling用以生成V-T波形，即[Rising Waveform]、[Falling Waveform]各兩組，描述暫態特性。Ron PU/PD impedance用以產生V-I波形，即[Pull-up]、[Pull-down]，描述穩態特性。

兩者在IBIS模型內分別有不同的作用[2]：V-T曲線描述了緩沖器切換後瞬態的輸出電壓。一般的IBIS緩沖器應都至少含有兩組在不同測試設置下所產生的VT波形。而V-I曲線可視為對上拉下拉電路通道上非線性電阻的描述。

2.3 Check Rising/Falling waveform of the IBIS generated by SPISim

[IBIS] \ [IBIS file(s) Inspector] to open the IBIS (spcmdl.ibs), which is just generated by SPIsim

Click [Rising Waveform] on the left-side of window, then select [Wvfm] on the center-top of window

2.4 Compare the IBIS generated by SPISim with the original generated by Micron

本章節所介紹的方法，自2021R2起有另外直接從Designer circuit開啟的捷徑

  1. 從SPICE模型生成IBIS模型

此流程適合於IC設計公司，用以產生一個與SPICE模型相同波形的IBIS模型。(支持IBIS 5.1 power-aware IBIS)

3.1 [IBIS] \ [Full IBIS modeling flow]

選擇Module Type 為 [MPro : General modeling/optimization]後的默認狀態即是

3.2 Select [From silicon design netlist] and SPICE solver to simulate

上圖步驟4可以指定使用AEDT內默認的Nexxim或其他(像HSPICE)的SPICE模擬引擎。

上圖步驟5所指向AEDT內默認的IBIS7 checker是IBIS.org的官方語法檢查器。

3.3 Assign the SPICE source files and define I/O pins

3.4 Simulation settings

If you set [Power aware modeling] True here, SPISim will generate IBIS model following IBIS5.1 automatically.

3.5 Validation items

3.6 IBIS model generation flow, step by step [3]

    The buttons of step15~21 will not be enable until the button of step14 is done.

    If the button of step14 is always inactive on your end, please close SPIsim and AEDT, re-open it will fix the problem.

    If you encounter error message to run the attached example in step17, please check if all the source SPICE files (Base.sp and ap7pm_18_mode.ibs) exist in the working floder (in the case, it is C:\temp)

    Button22 can export the setting configuration (SPICE_2_IBIS.cfg), which is able to re-use later by the [Browse]+[Import] buttons.

3.7 Check the waveform of SPICE input files after running step17 in section3.6

Step16 in section3.6 generates all SPICE deck files once as below :

The waveform of SPICE input files after running step17 in section3.6 are as below :

  1. 問題與討論

4.1 What does "Rfixture" parameter in step 2.2 mean?

Ans : You can find ibis spec. from ibis.org. In the spec, it has detailed explanation about RFixture… as shown below on P86 of the latest V7.0 spec. Basically it is a loading resistor outside package.

C_fixture單位是小寫pF(picofarads)不能寫成大寫PF(petafarads)。1 pF = 10-27 PF

C_fixture = 5p ... (O)

C_fixture = 5P ... (X)

4.2 How to generate IBIS with ODT(On-Die Terminator)?

Ans :

4.2.1 In step 2.2, set [On-die termination]=Rt(34)x2 and [IO type buffer]=False to generate an INPUT buffer with ODT 34 ohm.

    However, it only supports DDR2/DDR3 ODT, and not DDR4 ODT yet. [4]p.13-14

    4.2.2 To generate DDR4 IBIS with correct ODT behavior, please use [From silicon design netlist] flow at this moment.

4.3 How to generate differential IBIS model from SPICE netlist?

Ans :

4.4 IBIS內的波形有min/type/max三種corner，有些還有slow/fast，該如何理解?

Ans：Analog Device AN-715 [5]內有一段說明

    The models can be generated for three different corner conditions: typical, minimum, and maximum. In a typical model, the data will be obtained for nominal supply voltage, nominal temperature, and nominal process parameters; in a minimum model, the data will be obtained with the lowest supply voltage, high temperature, and weak process parameters; and for a maximum model, the conditions will be the highest supply voltage, low temperature, and strong process parameters.

    Each of these conditions leads to typical, slow, and fast models. A fast model is created by considering the highest current values with the fast transition time and the minimum package characteristics. On the other hand, the lowest current values with a slow transition time and maximum package values will produce a slow model.

    min指所有參數為min，max指所有參數為max

    slow指部分參數為min，部分參數為max，e.g. current min、temperature min、package parasitic max.

    fast指部分參數為min，部分參數為max，e.g. current max、temperature max、package parasitic min.

    (ANSYS Circuit online HELP內搜尋關鍵字"IBIS TYP"可以找到更清楚的列表)

  1. 參考

[1] 什麼是IBIS

[2] IBIS模型在模擬時是如何被運用的

[3] 如何建立IBIS模型

[4] "DDR4 Board Design and Signal Integrity Verification Challenges", DesignCon2015.

[5] Analog Device AN-715 p.2

[6] IBIS在考慮Power Supply Induced Jitter(PSIJ)的侷限與解決方案