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Home > ANSYS Simplorer教學 > Simplorer links VHDL-AMS
本文始於2018.08,以R19.1示範如何在Twin Builder (Simplorer)內使用VHDL-AMS Library. 本文所介紹的功能,需要有Twin Builder license.
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What is VHDL-AMS? [1]
A mixed-signal modeling language based on VHDL (IEEE 1076-1993)
A strict superset of VHDL (IEEE 1076.1-1999), AMS => Analog / Mixed Signal Extensions
Represents complex models directly
Can also model non-electrical physical phenomena
Select the model you are interested, right-click and press [Load Example] to understand how to use these models easily.
right-click the VHDL component in schematic window, and press [Edit Model] to view\edit the VHDL-AMS code.
[VHDL Model Editor] \ [Export Text As] , to export or save as another .vhd
[Tools] \ [Design Tools] \ [Create model and component from current schematic] is a useful function.
[Tools] \ [Pproject Tools] \ [Import Simplorer Models]
3.1 Use any text editor to edit a simple VHDL counter example (.vhd) as below
3.2 [Tools] \ [Pproject Tools] \ [Import Simplorer Models]
3.3 本例中,line25~28有四種寫法,Simplorer接受其中三種,但ModelSim支持四種全部
Scriptum : free VHDL and Verilog text editor
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Q&A
[1] Introduction To The VHDL-AMD Modeling Language, Scott Cooper, Mentor Graphics, 2007