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本文始於2021，介紹如何做Icepak-Simplorer (Twin Builder)系統熱分析。2+4步驟為Classic Icepak-Simplorer流程，3+4步驟為AEDT Icepak-Simplorer流程，兩者在2021R1.1(含)以後的版本可以得到一致的結果。
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System Thermal Analysis Flow
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Classic Icepak Settings -- create step response files in Icepak
2.1 Unpack .ztr field (an classic packed Icepak)
2.2 Setup State-Space trails for parameter optimization
2.3 Assign inputs and outputs for state-space
2.4 Run State-Space
- AEDT Icepak Settings -- create step response files in Icepak
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Simplorer Settings -- create ROM in Simplorer
4.1 Create a LTI ROM
4.2 Place LTI ROM
4.3 Enable outputs
4.4 Connect inputs
4.5 Setup and Run
4.6 Plot outputs
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Q&A
5.2 另一種匯入(生成)Icepak LTI ROM的方法
- Reference
3.1 Unpack .ztr field (an classic packed Icepak)
3.3 Run Steady-State Analysis First
3.4 Setup Transient Icepak with sources optimization
3.5 Run Transient Analysis and export LTI ROM
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System Thermal Analysis Flow
若我們考慮一塊PCB版上有四個熱源(可能是功率元件或CPU)，而這四個熱源在系統模擬時是時變的特性，那我們該如何透過Icepak+Simplorer (Twin Builder)實現這樣的系統模擬流程呢?
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Classic Icepak Settings -- create step response files in Icepak
2.1 Unpack .ztr field (a packed classic Icepak)
Install classic Icepak and set "Workbench path" in [Tools] \ [Options] \ [General options] \ [Miscellaneous] before you open the classic Icepack from AEDT at the first time.
2.2 Setup State-Space trails for parameter optimization
[Solve] \ [Run optimization]
2.3 Assign inputs and outputs for state-space
2.4 Run State-Space
Pree the green button [Run] showed above, to analysis "Steady state solution" first.
2.5 Run transient trails
Change [Steady state] to [Trancient] solution type
Press [Set] button to set optimetric sweep for these 5W power inputs
2.6 Step response files
Press the green button [Run trails] to run the transient analysis and export Icepak step response output data for each input powers FET1/FET2/FET3/FET4.
- AEDT Icepak Settings -- create step response files in Icepak
3.1 Unpack .ztr field (a packed classic Icepak)
[File] \ [Open]
3.2 Setup Steady-State Icepak
3.2.1 Add "Block" type thermal model for FET1, FET2, FET3, FET4 with Total Power assigned.
for 3D object (box).
"Source" type thermal model would get different result for this case. Suggest "Block" type thermal model
3.2.2 Add Thermal Monitor for FET1, FET2, FET3, FET4
The step is necessary. If you don't do it, you would not see output terminals in step 3.5.
3.3 Run Steady-State
Analysis First
3.4 Setup Transient Icepak with sources optimization
Copy the design in step 3.2 to another new design, and change to "Transient" solver type.
[Icepak] \ [Solution Type]
Add four variable(parameter) for each EFT total power first,
then use Toolkit to set optimetric sweep
[Icepak] \ [Toolkit] \ [Modeling] \ [LTI_ROM_Parametric_Setup]
- Simplorer Settings -- create ROM in Simplorer
In this section, we will use the step response data to create state-space ROM model in Simplorer.
4.1 Create a LTI ROM
[Twin Builder] \ [Toolkit] \ [Thermal Model Identification]
4.2 Place LTI ROM
4.3 Enable outputs
[Twin Builder] \ [Output Dialog...]
4.4 Connect inputs
set 1.5 value to "Constant"
set 1.5 amplitude and 50s period for "Trapezoidal Waveform"
4.5 Setup and Run
4.6 Plot outputs
3.5 Run Transient
Analysis and export LTI ROM
Run Transient "All" Analysis
[Icepak] \ [Export ROM] \ [LTI ROM]
上圖縱軸的的單位並非攝氏溫度(oC)，而是凱氏溫度(oK)。這單位由於是Icepak temperature monitor的輸出，目前無法更改，但使用者可以自行減去273.15換算成攝氏溫度。[oK]=[oC]+273.15
行文至此，不知道各位讀者心中是否有個疑問：這樣的模擬流程到底在系統閉迴路的熱模擬實務上怎麼應用?因為ROM的輸入只能是熱源的功率(不能是風扇的風速)，輸出只能是觀測點的溫度...只有這樣的功能不知有什路用
本文只是起手式，我們的目標是透過模擬評估實施不同的散熱對策下，如裸片IC/加散熱片/水冷裝置/風扇...等，電源模組的轉換效率/傳導干擾/輻射干擾 的差異。想要做到這樣的效果，還需要搭配Thermal-Aware Power Device Model與HFSS-Simplorer技術，敬請期待...
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Q&A
5.1 LTI ROM是什麼? 其特點為何?
Ans：LTI ROM means "Linear Time Invariant Reduced Order Model".
Icepak-Simplorer透過LTI ROM做系統模擬的最大好處是：以此例來說四顆FET開關(熱源)的溫度可能是固定或隨時間變化的，我們只要一開始分別把這四個熱源的變動組合掃過一次以求解出熱模型(ROM)，後續在做系統層級的熱模擬時就不需要再透過Icepak做耗時的co-simulation即可得到不同時間點、不同熱源組合變化下的系統真實熱分佈狀態，這功能實在太酷了。
5.2 另一種匯入(生成)Icepak LTI ROM的方法
Ans：步驟4.1, 4.2可以用以下另一種方式做
在完成步驟2.6或3.5後，Icepak工作路徑下會有一個xxx_LTIROM.aedtexport\xxx\
內含幾個xxx.out (Icepak out)與一個xxx.simpinfo (Icepak source file)
[Twin Builder] \ [SubCircuit] \ [Add Icepak Component...]
透過這一條路匯入的LTI ROM，模擬結果一樣
5.3 什麼原因導致在step3.5中Export LTI ROM時， 有時會只看到Input或Output項?
Ans：步驟 3.4對熱源瓦數的變數設定決定了input項，而步驟3.2.2的monitor項決定了output項。
5.4 必須先跑過穩態(steady state)再跑暫態(transient)，才能產生LTI ROM的原因是什麼?
Ans： 前者用以產生initial value
- Reference