The
article is intended to introduce how to optimize impedance of conductor
using Q3D Extractor v11 (SI2D).
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Review The Whole 3D Model
-
Cut Several
Cross-sections from Q3D
-
Copy These
Cross-sections to SI2D
-
Impedance Analysis in SI2D
-
Optimize Differential
Impedance
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問題與討論
6.1 為何不以看TDR為設計/分析connector特性阻抗的方法,而以切橫截面的方法分析?
-
Review The Whole 3D Model
1.1 PCIE connector
and PCB
1.2 PCIE connector
only
-
Cut Several
Cross-sections from Q3D
2.1 Select three
locations to cut the cross-sections
2.2 Move the
coordinate to the selected location
[Modeler]
\ [Coordinate
System] \ [Create]
\ [Relative
CS] \ [Offset]
2.3 Cut the
cross-section sheets
Remove all the
sheet in the project first.
Select all (Ctrl+A)
[Modeler]
\ [Surface]
\ [Section]
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Copy These
Cross-sections to SI2D
3.1 Cut 1, 2, 3
cross-sections as bellow
Re-name and set
color.
The yellow nets
means differential pairs, and the green nets means ground nets.
3.2 Move the
cross-section to the location Z=0, and create a new design in SI2D.
Create SI2D
,
and set solution type = [Open]
The cross-section in Q3D can't be copied to SI2D until it is
moved to the location Z=0.
3.3 Add air box
[Draw]
\ [Region]
Q3D don't need air box to solve, but SI2D need it
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Impedance Analysis in SI2D
4.1 Unit all the
ground pins
Select all the
green pins and [Modeler] \ [Boolean]
\ [unit]
4.2 Assign signal
nets, and reference ground
[2D
Extractor] \ [Conductor]
\ [Assign]
\ [Reference]
or
[Signal
Line]
4.3 Set
differential pairs
[2D
Extractor] \ [Reduce
Matrix] \ [Diff
Pair]
4.4 Add solution
setup
[2D
Extractor] \ [Analysis
Setup] \ [Add Solution
Setup]
此例是做特性阻抗分析,沒有要看電容C,但[Admittance
(Capacitance/Conductance)]不能不選。
4.5 Run analysis
4.6 Edit Source
[2D
Extractor] \ [Fields] \ [Edit
Sources]
4.7 Plot the E-field
Select the
sheet object to show E-field, and
[2D
Extractor] \ [Fields] \ [CG
Fields] \ [E] \ [VectorE]
4.8 Plot diff.
impedance result of cut 1, cut 2, and cut 3 cross-sections
[2D
Extractor] \ [Results]
\ [Solution Data]
At location cut_1, the
differential impedance 121 ohm is too large, and it has to be
optimized.
4.9 By the way, we
can repeat step3.1~4.8 to get the differential impedance at location
cut_2=142.8 ohm and
cut_3=110 ohm.
-
Optimize Differential
Impedance
Use cut_1 for
example to set the section width of pin conductor as a parameter,
which needs to be optimized
5.1 Select edges of
all pins
5.2 Move edge and
set it as a variable "mv_width"
[Modeler]
\ [Edge]
\ [Move
Edges]
5.3 Optimize
setting
[2D
Extractor] \ [Design
Properties]
[2D
Extractor] \ [Optimetrics
Analysis]
\ [Add Optimization]
[Acceptable Cost]將決定step5.4的最佳畫模擬結果,多接近[Goal]
value=100,此例我們設定100.1~99.9 ohm的範圍
[2D
Extractor] \ [Analyze All]
5.4 Optimized
Result
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問題與討論
6.1 為何不以看TDR為設計/分析connector特性阻抗的方法,而以切橫截面的方法分析?
Ans:看TDR雖然也可以看出傳輸線路徑上的特性阻抗變化,但用來做複雜結構的特性阻抗最佳化設計時,會遇到以下兩個問題
-- 僅能透過傳遞延遲時間概估特性阻抗發生變化的位置,對於重新設計機構再跑3D模擬,sweep參數最佳化,很沒效率
(位置抓不準)
-- 如果傳輸線本身的損耗較大,或是傳輸線之間的耦合影響較大(如距離很近的differential),造成TDR所打的step
function隨著傳播越遠,Tr變得越緩,不易看出傳輸路徑的中後段,較細微的特性阻抗變化(TDR解析度變差),這現象也稱作TDR
masking effect。
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